The present invention relates to digital sample rate converters (SRCs), and more particularly to improvements that reduce the amount of the computation required for the filtering and that improve the signal-to-noise ratio (SNR).
There are many applications in which is desirable to combine or mix a first stream of digital data (such as audio frequency data), which has been sampled at a first sample rate with a second stream of digital data that has been sampled at a second different sample rate and then digitally process the combined/mixed data. This cannot ordinarily be accomplished unless the sample rate of one of the two streams of digital data is converted by a digital sample rate converter to exactly match the sample rate of the other stream of digital data.
There are two primary known techniques for implementing digital sample rate converters (SRCs). The first and most common known technique involves sampling an input signal at an input rate, and then upsampling it by a first integer, performing appropriate anti-aliasing filtering, and then downsampling the filtered signal by a second integer to provide output data at the desired output sample rate. The integers used for determining up/down sampling factors are determined by the ratio of the output sample rate to the input sample rate, and may be large integers in some cases. The anti-alias filtering is needed to prevent images that are produced by the upsampling process from aliasing back into the desired passband of the output signal during the downsampling step. (in discrete-time signal processing, it is well known that images which are replicas of the main or fundamental signal are produced and become evident when a signal is upsampled. In effect, the images are versions of the original input signal frequency modulated by integer multiples of the original input sampling rate. For example, a signal that was initially sampled at 8 kHz and then was up-sampled by a factor of 4 to 32 kHz will have images of the input signal centered at 8 kHz and 16 kHz. Due to the cyclical, periodic nature of frequency in the discrete-time domain, images also appear at higher integer multiples of the input sampling rate.)
Implementations of sample rate converters using this approach typically take advantage of the upsampling and downsampling operations in order to reduce the amount of computation required by the anti-alias filtering. For example, assuming an upsampling integer equal to N, where N is greater than 1, the upsampled signal entering the anti-aliasing filter will have Nxe2x88x921 of every consecutive N samples equal to 0. Therefore, the filter implementation can avoid all summing or multiplying of these samples (i.e., the ones having a value of 0) with any other values, since the trivial result is already known. Assuming a downsampling integer is equal to M, where M is greater than 1, only 1 out of every M consecutive outputs from the filter will actually be used, and Mxe2x88x921 outputs of every M consecutive outputs will be discarded by the downsampling operation. Therefore, the amount of filter computation can be even further reduced by calculating only the outputs that will be used, but not calculating the outputs that will be eventually discarded. Taking advantage of both of these characteristics of a sample rate converter reduces the filter computation necessary without causing any modification to the effective signal processing actually being performed or to the final result.
The second known technique for implementing a digital SRC includes first upsampling an input signal to a very high rate and filtering it to reduce images. Then the point in time at which an output sample is required is calculated. This time-point generally falls between two values of the upsampled and filtered input. Next, an output sample is calculated by effectively xe2x80x9cresamplingxe2x80x9d the upsampled and filtered input using a suitable formula, such as by linearly interpolating between two adjacent upsampled and filtered input samples to generate the output sample, based on the time-point of the output sample and the time-points of the adjacent upsampled and filtered input samples.
U.S. Pat. Nos. 5,475,628, 5,666,299, 6,141,671 and 6,208,671 disclose exceedingly complex sample rate conversion circuitry and techniques which are generally are illustrative of the known techniques for implementing asynchronous digital sample rate converters. Also see pp. 100-115 of the text xe2x80x9cDiscrete-Time Signal Processingxe2x80x9d by Alan V. Oppenheim and Ronald W. Schafer, Prentice-Hall international, Inc. 1989. Also see the product specification sheet for the Analog Devices AD1896 192 kHz Stereo Asynchronous Sample Rate Converter.
There is an unmet need for an improved digital sample rate converter and method for reducing the amount of computation required for filtering operations.
There also is an unmet need for an improved digital sample rate converter and method wherein the amount of computation required to improve the signal-to-noise ratio of the sample rate converter is reduced.
There also is an unmet need for an improved digital sample rate converter and method wherein the amount of computation required for filtering operations is reduced and wherein the amount of computation required for improving the signal-to noise ratio of the sample rate converter is reduced.
There also is an unmet need for an improved digital sample rate converter and method which utilize digital arithmetic without use of any analog functions.
Accordingly, it is an object of the invention to provide an improved digital sample rate converter that reduces the amount of computation required for filtering operations.
It is another object of the invention to provide an improved digital rate sample converter that provides an improved signal-to-noise ratio.
It is another object of the invention to provide an improved digital sample rate converter that both reduces the amount of computation required for filtering operations and provides an improved signal-to-noise ratio.
It is another object of the invention to provide an improved digital sample rate converter and method which entirely utilize digital arithmetic, without use of any analog functions
Briefly described, and in accordance with one embodiment thereof, the invention provides a method in for converting a digital input signal (Din) having a first sample rate (Fs_in) to a corresponding digital output signal (Dout) having a second sample rate (Fs_out), including upsampling the digital input signal (Din) by an integer N to produce a first digital signal (X1) having a third sample rate (Fs_in*N), filtering the digital signal (X1) to produce a filtered, upsampled second digital signal (X3), computing a first value of a third digital signal (X6) based on the second digital signal (X3), filtering the third digital signal (X6) to produce a fourth digital signal (X7), and downsampling the fourth digital signal (X7) by an integer M to produce the digital output signal (Dout) at the second sample rate (Fs_out). A time difference (td) between a most recent sample value of the second digital signal (X3) and a most recent sample value of the third digital signal (X6) is calculated, and then a subsequent value of the third digital signal (X6) is calculated based on a current value of the second digital signal (X3) and the time difference (td).
In a described embodiment, the invention provides a digital sample rate converter that converts a digital input signal (Din) having a first sample rate (Fs_in) to a corresponding digital output signal (Dout) having a second sample rate (Fs_out). The digital sample rate converter includes an upsampling circuit (3) for upsampling the digital input signal (Din) to produce a first digital signal (X1) having a third sample rate (Fs_in*N) and a feedback algorithm circuit (23A) which calculates a time difference (td) between a most recent input sample value representative of the first digital signal (X1) and a most recent output sample value (X6) of the calculating means and also processes the time difference (td) to compute a next value of the output signal (Dout). An interpolation filter (5) is coupled to an output of the upsampling circuit (3) and filters the first digital signal (X1) to produce a second digital signal (X3). The feedback algorithm circuit (23A) receives the second digital signal (X3) for filtering and sample rate conversion of the second digital signal (X3) in order to produce a third digital signal (X6) having a fourth sample rate (Fs_out*M) which is a second predetermined factor (M) times the second sample rate (Fs_out). A decimation filter (17) is coupled to an output of the feedback algorithm circuit (23A) for producing a fourth digital signal (X7) in response to the third digital signal (X6), and a downsampling circuit (19) is coupled to the decimation filter which downed samples the fourth digital signal (X7) by a factor of M to produce the digital output signal (Dout) at the second sample rate (Fs_out).